Exemplary embodiments relate to an addressing circuit of a semiconductor memory device and a method for addressing and, more particularly, to an addressing circuit for assigning data to normal cell arrays including main cell arrays and redundant cell arrays.
In general, defective cell arrays, including, for example defective columns, are detected by testing semiconductor memory devices.
Generally, the defective cell array is repaired by first comparing an address of external input data and an address of a defective cell array. Then, if as a result of the comparison, the address of external input data is identical with the address of the defective cell array, the external input data is assigned to a redundant cell array.
In such a redundancy operation, because addresses are compared, more time for performing the redundancy operation may be required.